Using RustHDL

This section of the documentation covers the details of using RustHDL to generate firmware.

Here is an overview of the sections.

• bits - how to manage arbitrary bit-width signals
• operators - operations that are defined on signals
• signals - the struct used to represent a signal (wire) in the firmware
• traits - the traits used to implement RustHDL
• synthesizable - the synthesizable subset of Rust
• interfaces - how to simplify your designs with interfaces
• simulation - how to simulate your design in RustHDL
• high level synthesis - a high level synthesis library written in RustHDL
• loops - loops and arrays in RustHDL
• structs - using struct-valued signals in RustHDL
• verilog - generating Verilog from your RustHDL code
• wrapping - wrapping black box cores and other Verilog with your RustHDL code